(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory of a dynamic random access memory (DRAM) type having an asynchronous static random access memory (SRAM) interface.
(2) Description of the Related Art
In recent years, attention has been riveted to DRAMs (pseudo SRAMs) having an asynchronous SRAM interface because of low power consumption, the feasibility of large storage capacity, cheapness, and so on.
For example, Japanese Patent Laid-Open Publication No. 2002-118383 discloses a synchronous pseudo SRAM which performs refresh operation internally and automatically.
FIG. 7 is a view showing the structure of a conventional semiconductor memory of a pseudo SRAM type.
A semiconductor memory 20 comprises an ATD generation circuit 21, a REF control circuit 22, a REF-ACT comparison circuit 23, delay circuits 24a and 24b, a latch signal generation circuit 25, REF-add counters 26, input buffers 27, row-add latch circuits 28, column-add latch circuits 29, a core control circuit 30, and a memory cell array (Hereinafter referred to as core circuit) 31.
The ATD generation circuit 21 detects a change in external signal (/CE, /WE, /OE, or ADD) and generates an active request signal atdpz indicative of, for example, a read/write request. In this case, /CE, /WE, /OE, and ADD are a chip enable signal, write enable signal, output enable signal, and address signal, respectively, and are external signals.
The REF control circuit 22 includes a timer (not shown) and generates a refresh request signal srtz for periodically performing refresh operation.
The REF-ACT comparison circuit 23 compares a refresh request signal srtz and an active request signal atdpz. If the refresh request signal srtz was input prior to the active request signal atdpz, then the REF-ACT comparison circuit 23 outputs a refresh execution request signal refpz. If the active request signal atdpz was input prior to the refresh request signal srtz, then the REF-ACT comparison circuit 23 outputs an active execution request signal actpz.
The delay circuits 24a and 24b delay an active execution request signal actpz and a refresh execution request signal refpz, respectively, by time taken to define an internal address in the core circuit 31.
The latch signal generation circuit 25 outputs an external address import signal ealz in response to an active execution request signal actpz and outputs a refresh address import signal ialz in response to a refresh execution request signal refpz.
The REF-add counters 26 count up to automatically generate a refresh address rfa##z.
An address signal ADD specified by an active request is input to the input buffers 27 from the outside and the input buffers 27 output it as an external address a##z.
The row-add latch circuits 28 specify a row address in the direction of word lines (not shown) in the core circuit 31.
The column-add latch circuits 29 specify a column address in the direction of column lines (not shown) in the core circuit 31.
The core control circuit 30 controls the core circuit 31 with a core control signal corez.
The core circuit 31 is a memory cell array of a DRAM type.
FIG. 8 is a circuit diagram of a conventional REF-ACT comparison circuit.
The REF-ACT comparison circuit 23 includes inverters 300 through 310, NAND circuits 320 through 329, a pulse width expansion section 330, and delay circuits 331 through 333. The NAND circuits 321 and 322, 323 and 324, 325 and 326, and 327 and 328 makeup flip-flops FF10, FF11, FF12, and FF13 respectively. An active request signal atdpz is input to the pulse width expansion section 330 via the inverter 300. The pulse width of the active request signal atdpz is expanded here so that a period during which the active request signal atdpz is at the high level (H level) will match a period during which a core control signal corez output from the core control circuit 30 is at the H level, and is input to one input terminal of the NAND circuit 320. The core control signal corez is input to the other input terminal of the NAND circuit 320 via the inverter 301.
A refresh request signal srtz is input via the inverter 302 to one input terminal of the NAND circuit 321 included in the flip-flop FF10, and output from the NAND circuit 321 is input to one input terminal of the NAND circuit 324 included in the flip-flop FF11. Output from the NAND circuit 324 is output as a refresh execution request signal refpz via the inverter 303. Moreover, output from the inverter 303 is delayed by the delay circuit 331 and is input via the inverter 304 to one input terminal of the NAND circuit 322 included in the flip-flop FF10.
Furthermore, the output from the inverter 303 is input via the inverter 305 to one input terminal of the NAND circuit 325 included in the flip-flop FF12. The core control signal corez output from the core control circuit 30 is input to one input terminal of the other NAND circuit 326 included in the flip-flop FF12. Output from the NAND circuit 325, being output from the flip-flop FF12, is output as a refresh execution signal refz via the inverters 306 and 307. Moreover, output from the inverter 306 is input to one input terminal of the NAND circuit 329.
The active request signal atdpz is input to the delay circuit 332 via the inverter 308, is delayed by the delay circuit 332, and is input to one input terminal of the NAND circuit 327 included in the flip-flop FF13. Output from the NAND circuit 327, being output from the flip-flop FF13, is input to the other input terminal of the NAND circuit 329. Output from the NAND circuit 329 is output as an active execution request signal actpz via the inverter 309. Moreover, output from the inverter 309 is input to the delay circuit 333, is delayed there, and is input via the inverter 310 to one input terminal of the NAND circuit 328 included in the flip-flop FF13.
The delay circuit 331, inverter 304, and flip-flop FF10 shown in FIG. 8 are used for obtaining predetermined pulse width. The same applies to the delay circuit 333, inverter 310, and flip-flop FF13.
Now, operation in the conventional semiconductor memory 20 will be described with FIGS. 7 and 8.
FIG. 9 is a timing chart for describing operation performed in the conventional semiconductor memory in the case of refresh operation being performed prior to active operation.
Each arrow in FIG. 9 indicates a signal which changes in response to the rise or fall of another signal.
For example, when a chip enable signal /CE, being an external signal, is input to the ATD generation circuit 21, the ATD generation circuit 21 generates an active request signal atdpz. As shown in FIG. 9, in this case, the REF control circuit 22 generates a refresh request signal srtz before the active request signal atdpz is generated. The refresh request signal srtz and active request signal atdpz are input to the REF-ACT comparison circuit 23.
The refresh request signal srtz is at the H level, so potential at one input terminal of the NAND circuit 324 included in the flip-flop FF11 in the REF-ACT comparison circuit 23 becomes the H level. When the refresh request signal srtz goes into the H level, the active request signal atdpz and a core control signal corez are at the low level (L level). As a result, potential at one input terminal of the NAND circuit 323 included in the flip-flop FF11 becomes the L level. Therefore, output from the flip-flop FF11 goes into the L level and a refresh execution request signal refpz goes into the H level.
When the refresh execution request signal refpz goes into the H level, the latch signal generation circuit 25 generates a refresh address import signal ialz. Then a refresh address rfa##z is imported from the REF-add counters 26 and a row address ra##z where the core control circuit 30 refreshes data is specified.
Moreover, the refresh execution request signal refpz is delayed by the delay circuit 24b by time taken to define the row address ra##z in the core circuit 31 and is input to the core control circuit 30. When the core control circuit 30 receives the delayed refresh execution request signal refpz, it outputs the core control signal corez to refresh data stored in memory cells (not shown) in the core circuit 31 specified by the row address ra##z.
Data stored in memory cells connected to each of word lines (not shown) in the core circuit 31 is refreshed in block, so there is no need to specify a column address ca##z. Only a row address ra##z should be specified.
As shown in FIG. 9, it is assumed that the active request signal atdpz goes into the H level by the chip enable signal /CE just after the refresh request signal srtz being generated. If refresh operation is being performed and the core control signal corez is at the H level, a refresh execution signal refz and active execution request signal actpz are kept at the H and L levels respectively, as can be understood from FIG. 8. If the refresh execution request signal refpz goes into the L level and the core control signal corez goes into the L level, output from the flip-flop FF12 goes into the L level when the core control signal corez falls. Both the input terminals of the NAND circuit 329 go into the H level. As a result, the active execution request signal actpz goes into the H level. When the active execution request signal actpz goes into the H level, the latch signal generation circuit 25 outputs an external address import signal ealz. As a result, an external address a##z is imported from the input buffers 27 to the row-add latch circuits 28 and column-add latch circuits 29. Moreover, the active execution request signal actpz is delayed by the delay circuit 24a by time tA taken to define an address. Then the core control signal corez is put into the H level and a memory cell (not shown) specified by a row address ra##z and column address ca##z is accessed to perform active operation, such as writing or reading.
FIG. 10 is a timing chart for describing operation performed in the conventional semiconductor memory in the case of active operation being performed prior to refresh operation.
Each arrow in FIG. 10 indicates a signal which changes in response to the rise or fall of another signal.
For example, when a chip enable signal /CE, being an external signal, is input to the ATD generation circuit 21, the ATD generation circuit 21 generates an active request signal atdpz. As shown in FIG. 10, in this case, the ATD generation circuit 21 generates the active request signal atdpz before a refresh request signal srtz is generated. The refresh request signal srtz, the active request signal atdpz, and a core control signal corez are input to the REF-ACT comparison circuit 23.
When the active request signal atdpz is input to the REF-ACT comparison circuit 23, potential at one input terminal of the NAND circuit 323 included in the flip-flop FF11 shown in FIG. 8 becomes the H level. At this time, potential at one input terminal of the NAND circuit 324 included in the flip-flop FF11 becomes the L level, so output from the flip-flop FF11 goes into the H level. As a result, a refresh execution request signal refpz is kept at the L level and an active execution request signal actpz goes into the H level.
When the active execution request signal actpz goes into the H level, the latch signal generation circuit 25 generates an external address import signal ealz. As a result, an external address a##z is imported from the input buffers 27. The row-add latch circuits 28 and column-add latch circuits 29 specify a row address ra##z and column address ca##z respectively. Moreover, the active execution request signal actpz is delayed by the delay circuit 24a by time tA taken to define an internal address in the core circuit 31 and is input to the core control circuit 30. When the core control circuit 30 receives the active execution request signal actpz, it generates the core control signal corez and accesses a memory cell (not shown) in the core circuit 31 specified by the row address ra##z and column address ca##z to perform active operation, such as reading or writing.
As shown in FIG. 10, when the active operation is completed and the core control signal corez goes into the L level, the refresh execution request signal refpz goes into the H level in synchronization with the fall of the core control signal corez. When the refresh execution request signal refpz goes into the H level, the latch signal generation circuit 25 outputs a refresh address import signal ialz. As a result, the row-add latch circuits 28 import a refresh address rfa##z from the REF-add counters 26 to specify a row address ra##z.
Moreover, the refresh execution request signal refpz is delayed by the delay circuit 24b by time (tA) taken to define an internal address in the core circuit 31 and is input to the core control circuit 30. When the core control circuit 30 receives the delayed refresh execution request signal refpz, it outputs the core control signal corez to refresh data stored in memory cells (not shown) in the core circuit 31 specified by the row address.
As stated above, with the conventional semiconductor memory 20, a request for active operation, such as writing or reading, and a request for refresh operation are compared. If the request for refresh operation was made prior to the request for active operation, refresh operation is selected and then a refresh address is imported. That is to say, there is delay time tA between the selection of refresh operation and the definition of an internal address in the core circuit 31. This delays the refresh operation. Therefore, the active operation to be performed following the refresh operation is also delayed.
The present invention was made under the background circumstances as described above. An object of the present invention is to provide a semiconductor memory which can shorten refresh time.
In order to achieve the above object, a dynamic semiconductor memory having an asynchronous static semiconductor memory interface is provided. This semiconductor memory comprises a first comparison circuit for comparing a refresh request signal generated internally for performing refresh operation and an active request signal input from the outside for performing active operation and for immediately outputting a refresh address import signal in the case of the refresh request signal having been generated prior to the active request signal and a second comparison circuit for comparing a delayed refresh request signal obtained by delaying the refresh request signal by predetermined time and the active request signal, for outputting a refresh execution request signal in the case of the delayed refresh request signal having been input prior to the active request signal, and for outputting an active execution request signal in the case of the active request signal having been input prior to the delayed refresh request signal.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.